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| LH28F016SC-L/SCH-L LH28F016SC-L/SCH-L DESCRIPTION The LH28F016SC-L/SCH-L flash memories with SmartVoltage technology are high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. Their symmetrically-blocked architecture, flexible voltage and enhanced cycling capability provide for highly flexible component suitable for resident flash arrays, SIMMs and memory cards. Their enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F016SC-L/SCH-L offer three levels of protection : absolute protection with Vpp at GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs. 16 M-bit (2 MB x 8) SmartVoltage Flash Memories * Enhanced automated suspend options - Byte write suspend to read - Block erase suspend to byte write - Block erase suspend to read * Enhanced data protection features - Absolute protection with VPP = GND - Flexible block locking - Block erase/byte write lockout during power transitions * SRAM-compatible write interface * High-density symmetrically-blocked architecture - Thirty-two 64 k-byte erasable blocks * Enhanced cycling capability - 100 000 block erase cycles - 3.2 million block erase cycles/chip * Low power management - Deep power-down mode - Automatic power saving mode decreases ICC in static mode * Automated byte write and block erase - Command user interface - Status register * ETOXTM V nonvolatile flash technology * Packages - 40-pin TSOP Type I (TSOP040-P-1020) Normal bend/Reverse bend - 44-pin SOP (SOP044-P-0600) [LH28F016SC-L] - 48-ball CSP (FBGA048-P-0810) ETOX is a trademark of Intel Corporation. FEATURES * SmartVoltage technology - 2.7 V (Read-only), 3.3 V or 5 V VCC - 3.3 V, 5 V or 12 V VPP * High performance read access time LH28F016SC-L95/SCH-L95 - 95 ns (5.00.25 V)/100 ns (5.00.5 V)/ 120 ns (3.30.3 V)/150 ns (2.7 to 3.6 V) LH28F016SC-L12/SCH-L12 - 120 ns (5.00.5 V)/150 ns (3.30.3 V)/ 170 ns (2.7 to 3.6 V) COMPARISON TABLE VERSIONS LH28F016SC-L LH28F016SCH-L OPERATING TEMPERATURE 0 to +70C -40 to +85C DC CHARACTERISTICS VCC deep power-down current (MAX.) 10 A 20 A PACKAGE 40-pin TSOP (I), 44-pin SOP, 48-ball CSP 40-pin TSOP (I), 48-ball CSP In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. -1- LH28F016SC-L/SCH-L PIN CONNECTIONS 40-PIN TSOP (Type I) A19 A18 A17 A16 A15 A14 A13 A12 CE# VCC VPP RP# A11 A10 A9 A8 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 44-PIN SOP [LH28F016SC-L] TOP VIEW A20 NC WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC GND GND DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 VPP RP# A11 A10 A9 A8 A7 A6 A5 A4 NC NC A3 A2 A1 A0 DQ0 DQ1 DQ2 DQ3 GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 (TSOP040-P-1020) VCC CE# A12 A13 A14 A15 A16 A17 A18 A19 NC NC A20 NC WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC NOTE : Reverse bend available on request. (SOP044-P-0600) 48-BALL CSP H A5 A6 A4 A3 A1 A2 G A8 A9 A7 A0 DQ1 DQ0 F A11 RP# A10 DQ2 GND DQ3 E VPP NC NC NC NC GND D VCC NC NC NC NC VCC C A12 CE# A13 DQ6 DQ4 DQ5 B A15 A14 A16 RY/BY# A A18 1 A17 2 A19 3 A20 4 OE# 5 WE# 6 DQ7 NC (FBGA048-P-0810) -2- LH28F016SC-L/SCH-L BLOCK DIAGRAM DQ0-DQ7 OUTPUT BUFFER INPUT BUFFER OUTPUT MULTIPLEXER IDENTIFIER REGISTER DATA REGISTER I/O LOGIC VCC CE# STATUS REGISTER COMMAND USER INTERFACE WE# OE# RP# DATA COMPARATOR A0-A20 INPUT BUFFER Y DECODER Y GATING WRITE STATE MACHINE RY/BY# PROGRAM/ERASE VOLTAGE SWITCH VPP ADDRESS LATCH X DECODER 32 64 k-BYTE BLOCKS VCC GND ADDRESS COUNTER -3- LH28F016SC-L/SCH-L PIN DESCRIPTION SYMBOL A0-A20 TYPE INPUT NAME AND FUNCTION ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs DQ0-DQ7 INPUT/ OUTPUT data during memory array, status register, and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. CHIP ENABLE : Activates the device's control logic, input buffers, decoders, and sense CE# INPUT amplifiers. CE#-high deselects the device and reduces power consumption to standby levels. RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets internal automation. RP#-high enables normal operation. When driven low, RP# inhibits write operations which provide data protection during power transitions. Exit from deep RP# INPUT power-down sets the device to read array mode. RP# at VHH enables setting of the master lock-bit and enables configuration of block lock-bits when the master lock-bit is set. RP# = VHH overrides block lock-bits thereby enabling block erase and byte write operations to locked memory blocks. Block erase, byte write, or lock-bit configuration with VIH < RP# < VHH produce spurious results and should not be attempted. OE# WE# INPUT INPUT OUTPUT ENABLE : Gates the device's outputs during a read cycle. WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of the WE# pulse. READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is performing an internal operation (block erase, byte write, or lock-bit configuration). RY/BY# OUTPUT RY/BY#-high indicates that the WSM is ready for new commands, block erase is suspended, and byte write is inactive, byte write is suspended, or the device is in deep power-down mode. RY/BY# is always active and does not float when the chip is deselected or data outputs are disabled. BLOCK ERASE, BYTE WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY : For VPP SUPPLY erasing array blocks, writing bytes, or configuring lock-bits. With VPP VPPLK, memory contents cannot be altered. Block erase, byte write, and lock-bit configuration with an invalid VPP (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should not be attempted. DEVICE POWER SUPPLY : Internal detection configures the device for 2.7 V , 3.3 V or 5 V operation. To switch from one voltage to another, ramp VCC down to GND and then ramp VCC to the new voltage. Do not float any power pins. With VCC VLKO, all write VCC SUPPLY attempts to the flash memory are inhibited. Device operations at invalid VCC voltage (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should not be attempted. Block erase, byte write and lock-bit configuration operations with VCC < 3.0 V are not supported. GND NC SUPPLY GROUND : Do not float any ground pins. NO CONNECT : Lead is not internal connected; recommend to be floated. -4- LH28F016SC-L/SCH-L 1 INTRODUCTION This datasheet contains LH28F016SC-L/SCH-L specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. LH28F016SC-L/ SCH-L flash memories documentation also includes ordering information which is referenced in Section 7. arranged in thirty-two 64 k-byte blocks which are individually erasable, lockable, and unlockable insystem. The memory map is shown in Fig. 1. SmartVoltage technology provides a choice of VCC and VPP combinations, as shown in Table 1, to meet system performance and power expectations. 2.7 V VCC consumes approximately one-fifth the power of 5 V VCC and 3.3 V VCC consumes approximately one-fourth the power of 5 V VCC. But, 5 V VCC provides the highest read performance. VPP at 3.3 V and 5 V eliminates the need for a separate 12 V converter, while VPP = 12 V maximizes block erase and byte write performance. In addition to flexible erase and program voltages, the dedicated VPP pin gives complete data protection when VPP VPPLK. Table 1 VCC and VPP Voltage Combinations Offered by SmartVoltage Technology VCC VOLTAGE 2.7 V (NOTE 1) 3.3 V 5V VPP VOLTAGE -- 3.3 V, 5 V, 12 V 5 V, 12 V 1.1 New Features The LH28F016SC-L/SCH-L SmartVoltage flash memories maintain backwards-compatibility with the LH28F008SA. Key enhancements over the LH28F008SA include : * SmartVoltage Technology * Enhanced Suspend Capabilities * In-System Block Locking Both devices share a compatible pinout, status register, and software command set. These similarities enable a clean upgrade from the LH28F008SA to LH28F016SC-L/SCH-L. When upgrading, it is important to note the following differences : * Because of new feature support, the two devices have different device codes. This allows for software optimization. * VPPLK has been lowered from 6.5 V to 1.5 V to support 3.3 V and 5 V block erase, byte write, and lock-bit configuration operations. Designs that switch VPP off during read operations should make sure that the VPP voltage transitions to GND. * To take advantage of SmartVoltage technology, allow VPP connection to 3.3 V or 5 V. NOTE : 1. Block erase, byte write and lock-bit configuration operations with VCC < 3.0 V are not supported. Internal VCC and VPP detection circuitry automatically configures the device for optimized read and write operations. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, byte write, and lock-bit configuration operations. A block erase operation erases one of the device's 64 k-byte blocks typically within 1 second (5 V VCC, 1.2 Product Overview The LH28F016SC-L/SCH-L are high-performance 16 M-bit SmartVoltage flash memories organized as 2 M-byte of 8 bits. The 2 M-byte of data is -5- LH28F016SC-L/SCH-L 12 V VPP) independent of other blocks. Each block can be independently erased 100 000 times (3.2 million block erases per device). Block erase suspend mode allows system software to suspend block erase to read data from, or write data to any other block. Writing memory data is performed in byte increments typically within 6 s (5 V VCC, 12 V VPP). Byte write suspend mode enables the system to read data from, or write data to any other flash memory array location. Individual block locking uses a combination of bits, thirty-two block lock-bits and a master lock-bit, to lock and unlock blocks. Block lock-bits gate block erase and byte write operations, while the master lock-bit gates block lock-bit modification. Lock-bit configuration operations (Set Block Lock-Bit, Set Master Lock-Bit, and Clear Block Lock-Bits commands) set and cleared lock-bits. The status register indicates when the WSM's block erase, byte write, or lock-bit configuration operation is finished. The RY/BY# output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status polling using RY/BY# minimizes both CPU overhead and system power consumption. When low, RY/BY# indicates that the WSM is performing a block erase, byte write, or lock-bit configuration. RY/BY#-high indicates that the WSM is ready for a new command, block erase is suspended (and byte write is inactive), byte write is suspended, or the device is in deep power-down mode. The access time is 95 ns (tAVQV) at the VCC supply voltage range of 4.75 to 5.25 V over the temperature range, 0 to +70C (LH28F016SC-L)/ -40 to +85C (LH28F016SCH-L). At 4.5 to 5.5 V VCC, the access time is 100 ns or 120 ns. At lower VCC voltage, the access time is 120 ns or 150 ns (3.0 to 3.6 V) and 150 ns or 170 ns (2.7 to 3.6 V). The Automatic Power Saving (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical ICCR current is 1 mA at 5 V VCC and 3 mA at 2.7 V and 3.3 V VCC. When CE# and RP# pins are at VCC, the ICC CMOS standby mode is enabled. When the RP# pin is at GND, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHEL) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared. -6- LH28F016SC-L/SCH-L 2 PRINCIPLES OF OPERATION 1FFFFF 1F0000 1EFFFF 1E0000 1DFFFF 1D0000 1CFFFF 1C0000 1BFFFF 1B0000 1AFFFF 1A0000 19FFFF 190000 18FFFF 180000 17FFFF 170000 16FFFF 160000 15FFFF 150000 14FFFF 140000 13FFFF 130000 12FFFF 120000 11FFFF 110000 10FFFF 100000 0FFFFF 0F0000 0EFFFF 0E0000 0DFFFF 0D0000 0CFFFF 0C0000 0BFFFF 0B0000 0AFFFF 0A0000 09FFFF 090000 08FFFF 080000 07FFFF 070000 06FFFF 060000 05FFFF 050000 04FFFF 040000 03FFFF 030000 02FFFF 020000 01FFFF 010000 00FFFF 000000 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The LH28F016SC-L/SCH-L SmartVoltage flash memories include an on-chip WSM to manage block erase, byte write, and lock-bit configuration functions. It allows for : 100% TTL-level control inputs, fixed power supplies during block erasure, byte write, and lock-bit configuration, and minimal processor overhead with RAM-like interface timings. After initial device power-up or return from deep power-down mode (see Table 2 "Bus Operations"), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby, and output disable operations. Status register and identifier codes can be accessed through the CUI independent of the VPP voltage. High voltage on VPP enables successful block erasure, byte writing, and lock-bit configuration. All functions associated with altering memory contents--block erase, byte write, lock-bit configuration, status, and identifier codes--are accessed via the CUI and verified through the status register. Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase, byte write, and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latched during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes, or outputs status register data. Interface software that initiates and polls progress of block erase, byte write, and lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system Fig. 1 Memory Map -7- LH28F016SC-L/SCH-L software to suspend a block erase to read/write data from/to blocks other than that which is suspended. Byte write suspend allows system software to suspend a byte write to read data from any other flash memory array location. in and out of the component : CE#, OE#, WE#, and RP#. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control, and when active enables the selected memory device. OE# is the data output (DQ0-DQ7) control and when active drives the selected memory data onto the I/O bus. WE# must be at VIH and RP# must be at VIH or VHH. Fig. 13 illustrates a read cycle. 2.1 Data Protection Depending on the application, the system designer may choose to make the VPP power supply switchable (available only when memory block erases, byte writes, or lock-bit configurations are required) or hardwired to VPPH1/2/3. The device accommodates either design practice and encourages optimization of the processor-memory interface. When VPP VPPLK, memory contents cannot be altered. The CUI, with two-step block erase, byte write, or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to VPP. All write functions are disabled when VCC is below the write lockout voltage VLKO or when RP# is at VIL. The device's block locking capability provides additional protection from inadvertent code or data alteration by gating erase and byte write operations. 3.2 Output Disable With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0-DQ7 are placed in a high-impedance state. 3.3 Standby CE# at a logic-high level (VIH) places the device in standby mode which substantially reduces device power consumption. DQ0-DQ7 outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, byte write, or lock-bit configuration, the device continues functioning, and consuming active power until the operation completes. 3.4 Deep Power-Down RP# at VIL initiates the deep power-down mode. 3 BUS OPERATION The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. RP# must be held low for a minimum of 100 ns. Time tPHQV is required after return from power-down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H. During block erase, byte write, or lock-bit configuration modes, RP#-low will abort the operation. RY/BY# remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be 3.1 Read Information can be read from any block, identifier codes, or status register independent of the VPP voltage. RP# can be at either VIH or VHH. The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes, or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep powerdown mode, the device automatically resets to read array mode. Four control pins dictate the data flow -8- LH28F016SC-L/SCH-L partially erased or written. Time tPHWL is required after RP# goes to logic-high (VIH) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, byte write, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARP's flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. 3.5 Read Identifier Codes Operation The read identifier codes operation outputs the manufacture code, device code, block lock configuration codes for each block, and the master lock configuration code (see Fig. 2). Using the manufacture and device codes, the system CPU can automatically match the device with its proper algorithms. The block lock and master lock configuration codes identify locked and unlocked blocks and master lock-bit setting. 1FFFFF 1F0004 1F0003 1F0002 1F0001 1F0000 Reserved for Future Implementation Block 31 Lock Configuration Code Reserved for Future Implementation Block 31 (Blocks 2 through 30) 01FFFF 010004 010003 010002 010001 010000 00FFFF Reserved for Future Implementation Block 1 Lock Configuration Code Reserved for Future Implementation Block 1 Reserved for Future Implementation 000004 000003 000002 000001 000000 Master Lock Configuration Code Block 0 Lock Configuration Code Device Code Manufacture Code Block 0 Fig. 2 Device Identifier Code Memory Map -9- LH28F016SC-L/SCH-L 3.6 Write location. It is written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Fig. 14 and Fig. 15 illustrate WE# and CE#-controlled write operations. Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When VPP = VPPH1/2/3, the CUI additionally controls block erasure, byte write, and lock-bit configuration. The Block Erase command requires appropriate command data and an address within the block to be erased. The Byte Write command requires the command and address of the location to be written. Set Master and Block Lock-Bit commands require the command and address within the device (Master Lock) or block within the device (Block Lock) to be locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory 4 COMMAND DEFINITIONS When the VPP voltage VPPLK, read operations from the status register, identifier codes, or blocks are enabled. Placing VPPH1/2/3 on VPP enables successful block erase, byte write and lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. Table 3 defines these commands. Table 2 Bus Operations MODE Read Output Disable Standby Deep Power-Down Read Identifier Codes Write NOTE RP# CE# VIL VIL VIH X VIL VIL OE# VIL VIH X X VIL VIH 5. 6. WE# VIH VIH X X VIH VIL ADDRESS X X X X See Fig. 2 X VPP X X X X X X DQ0-7 DOUT High Z High Z High Z (NOTE 5) DIN RY/BY# X X X VOH VOH X 1, 2, 3, 8 VIH or VHH 3 VIH or VHH 3 4 8 VIH or VHH VIL VIH or VHH 3, 6, 7, 8 VIH or VHH NOTES : 1. Refer to Section 6.2.3 "DC CHARACTERISTICS". When VPP VPPLK, memory contents can be read, but not altered. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2/3 for VPP. See Section 6.2.3 "DC CHARACTERISTICS" for VPPLK and VPPH1/2/3 voltages. RY/BY# is VOL when the WSM is executing internal block erase, byte write, or lock-bit configuration algorithms. It is VOH during when the WSM is not busy, in block erase suspend mode (with byte write inactive), byte write suspend mode, or deep power-down mode. RP# at GND0.2 V ensures the lowest deep powerdown current. See Section 4.2 for read identifier code data. Command writes involving block erase, byte write, or lock-bit configuration are reliably executed when VPP = VPPH1/2/3 and VCC = VCC2/3/4. Block erase, byte write, or lock-bit configuration with VCC < 3.0 V or VIH < RP# < VHH produce spurious results and should not be attempted. Refer to Table 3 for valid DIN during a write operation. Don't use the timing both OE# and WE# are VIL. 2. 3. 7. 8. 4. - 10 - LH28F016SC-L/SCH-L Table 3 Command Definitions (NOTE 9) COMMAND Read Array/Reset Read Identifier Codes Read Status Register Clear Status Register Block Erase Byte Write Block Erase and Byte Write Suspend Block Erase and Byte Write Resume Set Block Lock-Bit Set Master Lock-Bit Clear Block Lock-Bits BUS CYCLES REQ'D. 1 2 2 1 2 2 1 1 2 2 2 5 5, 6 5 5 7 7 8 NOTE FIRST BUS CYCLE SECOND BUS CYCLE Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3) Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3) Write X FFH Write Write Write Write Write Write Write Write Write Write 6. 7. 4 X X X BA WA X X BA X X 90H 70H 50H 20H 40H or 10H B0H D0H 60H 60H 60H Read Read Write Write IA X BA WA ID SRD D0H WD Write Write Write BA X X 01H F1H D0H NOTES : 1. 2. Bus operations are defined in Table 2. X = Any valid address within the device. IA = Identifier code address : see Fig. 2. BA = Address within the block being erased or locked. WA = Address of memory location to be written. SRD = Data read from status register. See Table 6 for a description of the status register bits. WD = Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). ID = Data read from identifier codes. Following the Read Identifier Codes command, read operations access manufacture, device, block lock, and master lock codes. See Section 4.2 for read identifier code data. If the block is locked, RP# must be at VHH to enable block erase or byte write operations. Attempts to issue a block erase or byte write to a locked block while RP# is VIH. Either 40H or 10H is recognized by the WSM as the byte write setup. If the master lock-bit is set, RP# must be at VHH to set a block lock-bit. RP# must be at VHH to set the master lock-bit. If the master lock-bit is not set, a block lock-bit can be set while RP# is VIH. If the master lock-bit is set, RP# must be at VHH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is VIH. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. 3. 8. 4. 9. 5. - 11 - LH28F016SC-L/SCH-L 4.1 Read Array Command 4.3 Read Status Register Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, byte write or lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend or Byte Write Suspend command. The Read Array command functions independently of the VPP voltage and RP# can be VIH or VHH. The status register may be read to determine when a block erase, byte write, or lock-bit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE# or CE#, whichever occurs. OE# or CE# must toggle to VIH before further reads to update the status register latch. The Read Status Register command functions independently of the VPP voltage. RP# can be VIH or VHH. 4.2 Read Identifier Codes Command 4.4 Clear Status Register Command Status register bits SR.5, SR.4, SR.3, and SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 6). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied VPP voltage. RP# can be VIH or VHH. This command is not functional during block erase or byte write suspend modes. The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Fig. 2 retrieve the manufacture, device, block lock configuration and master lock configuration codes (see Table 4 for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the VPP voltage and RP# can be VIH or VHH. Following the Read Identifier Codes command, the following information can be read : Table 4 Identifier Codes CODE Manufacture Code Device Code Block Lock Configuration * Block is Unlocked * Block is Locked * Reserved for Future Use Master Lock Configuration * Device is Unlocked * Device is Locked * Reserved for Future Use ADDRESS 00000H 00001H X0002H (NOTE 1) DATA 89 AA DQ0 = 0 DQ0 = 1 DQ1-7 00003H DQ0 = 0 DQ0 = 1 DQ1-7 4.5 Block Erase Command NOTE : 1. X selects the specific block lock configuration code to be read. See Fig. 2 for the device identifier code memory map. Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by a block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, - 12 - LH28F016SC-L/SCH-L the device automatically outputs status register data when read (see Fig. 3). The CPU can detect block erase completion by analyzing the output data of the RY/BY# pin or status register bit SR.7. When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable block erasure can only occur when VCC = VCC2/3/4 and VPP = VPPH1/2/3. In the absence of this high voltage, block contents are protected against erasure. If block erase is attempted while VPP VPPLK, SR.3 and SR.5 will be set to "1". Successful block erase requires that the corresponding block lock-bit be cleared or, if set, that RP# = VHH. If block erase is attempted when the corresponding block lock-bit is set and RP# = VIH, SR.1 and SR.5 will be set to "1". Block erase operations with VIH < RP# < VHH produce spurious results and should not be attempted. When byte write is complete, status register bit SR.4 should be checked. If byte write error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it receives another command. Reliable byte writes can only occur when VCC = VCC2/3/4 and VPP = VPPH1/2/3. In the absence of this high voltage, memory contents are protected against byte writes. If byte write is attempted while VPP VPPLK, status register bits SR.3 and SR.4 will be set to "1". Successful byte write requires that the corresponding block lock-bit be cleared or, if set, that RP# = VHH. If byte write is attempted when the corresponding block lock-bit is set and RP# = VIH, SR.1 and SR.4 will be set to "1". Byte write operations with VIH < RP# < VHH produce spurious results and should not be attempted. 4.7 Block Erase Suspend Command 4.6 Byte Write Command Byte write is executed by a two-cycle command sequence. Byte write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the byte write and write verify algorithms internally. After the byte write sequence is written, the device automatically outputs status register data when read (see Fig. 4). The CPU can detect the completion of the byte write event by analyzing the RY/BY# pin or status register bit SR.7. The Block Erase Suspend command allows block erase interruption to read or byte write data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase operation has been suspended (both will be set to "1"). RY/BY# will also transition to VOH. Specification tWHRH2 defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Byte Write command sequence can also be issued during erase suspend to program data in other blocks. Using the Byte - 13 - LH28F016SC-L/SCH-L Write Suspend command (see Section 4.8), a byte write operation can also be suspended. During a byte write operation with block erase suspended, status register bit SR.7 will return to "0" and the RY/BY# output will transition to VOL. However, SR.6 will remain "1" to indicate block erase suspend status. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to VOL. After the Erase Resume command is written, the device automatically outputs status register data when read (see Fig. 5). VPP must remain at VPPH1/2/3 (the same VPP level used for block erase) while block erase is suspended. RP# must also remain at VIH or VHH (the same RP# level used for block erase). Block erase cannot resume until byte write operations initiated during block erase suspend have completed. commands while byte write is suspended are Read Status Register and Byte Write Resume. After Byte Write Resume command is written to the flash memory, the WSM will continue the byte write process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY# will return to VOL. After the Byte Write Resume command is written, the device automatically outputs status register data when read (see Fig. 6). VPP must remain at VPPH1/2/3 (the same VPP level used for byte write) while in byte write suspend mode. RP# must also remain at VIH or VHH (the same RP# level used for byte write). 4.9 Set Block and Master Lock-Bit Commands 4.8 Byte Write Suspend Command The Byte Write Suspend command allows byte write interruption to read data in other flash memory locations. Once the byte write process starts, writing the Byte Write Suspend command requests that the WSM suspend the byte write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Byte Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the byte write operation has been suspended (both will be set to "1"). RY/BY# will also transition to VOH. Specification tWHRH1 defines the byte write suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits and a master lock-bit. The block lock-bits gate program and erase operations while the master lock-bit gates block-lock bit modification. With the master lock-bit not set, individual block lock-bits can be set using the Set Block Lock-Bit command. The Set Master Lock-Bit command, in conjunction with RP# = VHH, sets the master lock-bit. After the master lock-bit is set, subsequent setting of block lock-bits requires both the Set Block Lock-Bit command and VHH on the RP# pin. See Table 5 for a summary of hardware and software write protection options. Set block lock-bit and master lock-bit are executed by a two-cycle command sequence. The set block or master lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked) or the set master lock-bit confirm (and any device address). The WSM then controls the set lock-bit algorithm. After the sequence is written, the device automatically outputs status register data when read (see Fig. 7). The CPU can detect the completion of the set lockbit event by analyzing the RY/BY# pin output or status register bit SR.7. - 14 - LH28F016SC-L/SCH-L When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set. An invalid Set Block or Master Lock-Bit command will result in status register bits SR.4 and SR.5 being set to "1". Also, reliable operations occur only when VCC = VCC2/3/4 and VPP = VPPH1/2/3. In the absence of this high voltage, lockbit contents are protected against alteration. A successful set block lock-bit operation requires that the master lock-bit be cleared or, if the master lock-bit is set, that RP# = VHH. If it is attempted with the master lock-bit set and RP# = VIH, SR.1 and SR.4 will be set to "1" and the operation will fail. Set block lock-bit operations while VIH < RP# < VHH produce spurious results and should not be attempted. A successful set master lock-bit operation requires that RP# = VHH. If it is attempted with RP# = VIH, SR.1 and SR.4 will be set to "1" and the operation will fail. Set master lock-bit operations with VIH < RP# < VHH produce spurious results and should not be attempted. written, the device automatically outputs status register data when read (see Fig. 8). The CPU can detect completion of the clear block lock-bits event by analyzing the RY/BY# pin output or status register bit SR.7. When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bits error is detected, the status register should be cleared. The CUI will remain in read status register mode until another command is issued. This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block LockBits command sequence will result in status register bits SR.4 and SR.5 being set to "1". Also, a reliable clear block lock-bits operation can only occur when VCC = VCC2/3/4 and VPP = VPPH1/2/3. If a clear block lock-bits operation is attempted while VPP VPPLK, SR.3 and SR.5 will be set to "1". In the absence of this high voltage, the block lock-bit contents are protected against alteration. A successful clear block lock-bits operation requires that the master lock-bit is not set or, if the master lock-bit is set, that RP# = VHH. If it is attempted with the master lock-bit set and RP# = VIH, SR.1 and SR.5 will be set to "1" and the operation will fail. A clear block lock-bits operation with VIH < RP# < VHH produce spurious results and should not be attempted. If a clear block lock-bits operation is aborted due to VPP or VCC transition out of valid range or RP# active transition, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. Once the master lock-bit is set, it cannot be cleared. 4.10 Clear Block Lock-Bits Command All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With the master lock-bit not set, block lock-bits can be cleared using only the Clear Block Lock-Bits command. If the master lock-bit is set, clearing block lock-bits requires both the Clear Block Lock-Bits command and VHH on the RP# pin. See Table 5 for a summary of hardware and software write protection options. Clear block lock-bits operation is executed by a two-cycle command sequence. A clear block lockbits setup is first written. After the command is - 15 - LH28F016SC-L/SCH-L Table 5 Write Protection Alternatives OPERATION Block Erase or Byte Write Set Block Lock-Bit Set Master Lock-Bit Clear Block Lock-Bits MASTER BLOCK RP# EFFECT LOCK-BIT LOCK-BIT 0 VIH or VHH Block Erase and Byte Write Enabled X 0 1 X 0 1 1 X X X X X VIH VHH VIH VHH VIH VHH VIH VHH Block is Locked. Block Erase and Byte Write Disabled Block Lock-Bit Override. Block Erase and Byte Write Enabled Master Lock-Bit is Set. Set Block Lock-Bit Disabled Master Lock-Bit Override. Set Block Lock-Bit Enabled Set Master Lock-Bit Disabled Set Master Lock-Bit Enabled Master Lock-Bit is Set. Clear Block Lock-Bits Disabled Master Lock-Bit Override. Clear Block Lock-Bits Enabled VIH or VHH Set Block Lock-Bit Enabled VIH or VHH Clear Block Lock-Bits Enabled Table 6 Status Register Definition WSMS 7 ESS 6 ECLBS 5 BWSLBS 4 VPPS 3 NOTES : BWSS 2 DPS 1 R 0 SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS (ESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed Check RY/BY# or SR.7 to determine block erase, byte write, or lock-bit configuration completion. SR.6-0 are invalid while SR.7 = "0". If both SR.5 and SR.4 are "1"s after a block erase or lock-bit configuration attempt, an improper command sequence was entered. SR.5 = ERASE AND CLEAR LOCK-BITS STATUS (ECLBS) SR.3 does not provide a continuous indication of VPP level. 1 = Error in Block Erase or Clear Lock-Bits The WSM interrogates and indicates the VPP level only after 0 = Successful Block Erase or Clear Lock-Bits Block Erase, Byte Write, Set Block/Master Lock-Bit, or Clear SR.4 = BYTE WRITE AND SET LOCK-BIT STATUS (BWSLBS) 1 = Error in Byte Write or Set Master/Block Lock-Bit 0 = Successful Byte Write or Set Master/Block Lock-Bit SR.3 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK SR.2 = BYTE WRITE SUSPEND STATUS (BWSS) 1 = Byte Write Suspended 0 = Byte Write in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) Block Lock-Bits command sequences. SR.3 is not guaranteed to reports accurate feedback only when VPP VPPH1/2/3. SR.1 does not provide a continuous indication of master and block lock-bit values. The WSM interrogates the master lockbit, block lock-bit, and RP# only after Block Erase, Byte Write, or Lock-Bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set, master lock-bit is set, and/or RP# is not VHH. Reading the block lock and master lock configuration codes after writing the Read Identifier Codes command indicates master and block lock-bit status. 1 = Master Lock-Bit, Block Lock-Bit and/or RP# SR.0 is reserved for future use and should be masked out Lock Detected, Operation Abort 0 = Unlock SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) when polling the status register. - 16 - LH28F016SC-L/SCH-L Start BUS OPERATION COMMAND Write Write Erase Setup Erase Confirm COMMENTS Data = 20H Addr = Within Block to be Erased Data = D0H Addr = Within Block to be Erased Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Write 20H, Block Address Write D0H, Block Address Read Standby Read Status Register No 0 SR.7 = 1 Full Status Check if Desired Suspend Block Erase Loop Yes Repeat for subsequent block erasures. Full status check can be done after each block erase or after a sequence of block erasures. Write FFH after the last block erase operation to place device in read array mode. Suspend Block Erase Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) BUS OPERATION COMMAND Standby COMMENTS Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect RP# = VIH, Block Lock-Bit is Set Only required for systems implementing lock-bit configuration Check SR.4, 5 Both 1 = Command Sequence Error Check SR.5 1 = Block Erase Error SR.3 = 0 1 VPP Range Error Standby SR.1 = 0 1 Device Protect Error Standby Standby SR.4, 5 = 0 1 Command Sequence Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple blocks are erased before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery. SR.5 = 0 Block Erase Successful 1 Block Erase Error Fig. 3 Automated Block Erase Flowchart - 17 - LH28F016SC-L/SCH-L Start BUS OPERATION COMMAND Write Write Setup Byte Write Byte Write COMMENTS Data = 40H Addr = Location to be Written Data = Data to be Written Addr = Location to be Written Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Write 40H, Address Write Byte Data and Address Read Standby Read Status Register No 0 SR.7 = 1 Full Status Check if Desired Suspend Byte Write Loop Yes Repeat for subsequent byte writes. SR full status check can be done after each byte write or after a sequence of byte writes. Write FFH after the last byte write operation to place device in read array mode. Suspend Byte Write Byte Write Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) BUS OPERATION COMMAND Standby COMMENTS Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect RP# = VIH, Block Lock-Bit is Set Only required for systems implementing lock-bit configuration Check SR.4 1 = Data Write Error SR.3 = 0 1 VPP Range Error Standby SR.1 = 0 1 Device Protect Error Standby SR.4 = 0 Byte Write Successful 1 Byte Write Error SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are written before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery. Fig. 4 Automated Byte Write Flowchart - 18 - LH28F016SC-L/SCH-L Start BUS OPERATION Write COMMAND Erase Suspend COMMENTS Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.6 1 = Block Erase Suspended 0 = Block Erase Completed Write B0H Read Read Status Register Standby SR.7 = 1 SR.6 = 1 Read Read or Byte Write? 0 Standby Erase Resume Write Data = D0H Addr = X 0 Block Erase Completed Byte Write Read Array Data Byte Write Loop No Done? Yes Write D0H Write FFH Block Erase Resumed Read Array Data Fig. 5 Block Erase Suspend/Resume Flowchart - 19 - LH28F016SC-L/SCH-L Start BUS OPERATION Write COMMAND Byte Write Suspend COMMENTS Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.2 1 = Byte Write Suspended 0 = Byte Write Completed Write B0H Read Read Status Register Standby 0 SR.7 = 1 SR.2 = 1 Write FFH 0 Byte Write Completed Standby Write Read Write Read Array Data = FFH Addr = X Read array locations other than that being written. Byte Write Resume Data = D0H Addr = X Read Array Data Done Reading Yes Write D0H No Write FFH Byte Write Resumed Read Array Data Fig. 6 Byte Write Suspend/Resume Flowchart - 20 - LH28F016SC-L/SCH-L Start BUS OPERATION COMMAND Set Block/Master Lock-Bit Setup Set Block or Master Lock-Bit Confirm COMMENTS Data = 60H Addr = Block Address (Block), Device Address (Master) Data = 01H (Block), F1H (Master) Addr = Block Address (Block), Device Address (Master) Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Write 60H, Block/Device Address Write Write 01H/F1H, Block/Device Address Write Read Status Register Read Standby 0 SR.7 = 1 Full Status Check if Desired Repeat for subsequent lock-bit set operations. Full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations. Write FFH after the last lock-bit set operation to place device in read array mode. Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) BUS OPERATION COMMAND Standby COMMENTS Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect RP# = VIH (Set Master Lock-Bit Operation) RP# = VIH, Master Lock-Bit is Set (Set Block Lock-Bit Operation) Check SR.4, 5 Both 1 = Command Sequence Error Check SR.4 1 = Set Lock-Bit Error SR.3 = 0 1 VPP Range Error Standby SR.1 = 0 1 Device Protect Error Standby SR.4, 5 = 0 1 Command Sequence Error Standby SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple lock-bits are set before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery. SR.4 = 0 Set Lock-Bit Successful 1 Set Lock-Bit Error Fig. 7 Set Block and Master Lock-Bit Flowchart - 21 - LH28F016SC-L/SCH-L Start BUS OPERATION Write COMMAND Clear Block Lock-Bits Setup Clear Block Lock-Bits Confirm COMMENTS Data = 60H Addr = X Data = D0H Addr = X Write 60H Write Write D0H Read Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Read Status Register Standby SR.7 = 1 0 Write FFH after the last clear block lock-bits operation to place device in read array mode. Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) BUS OPERATION COMMAND Standby COMMENTS Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect RP# = VIH, Master Lock-Bit is Set Check SR.4, 5 Both 1 = Command Sequence Error Check SR.5 1 = Clear Block Lock-Bits Error 1 SR.3 = 0 1 Device Protect Error Standby Standby VPP Range Error Standby SR.1 = 0 1 SR.4, 5 = 0 1 Command Sequence Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command. If error is detected, clear the status register before attempting retry or other error recovery. SR.5 = 0 Clear Block Lock-Bits Error Clear Block Lock-Bits Successful Fig. 8 Clear Block Lock-Bits Flowchart - 22 - LH28F016SC-L/SCH-L 5 DESIGN CONSIDERATIONS 5.1 Three-Line Output Control issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of CE# and OE#. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 F ceramic capacitor connected between its VCC and GND and between its VPP and GND. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 F electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance. The device will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Three-line control provides for : a. Lowest possible memory power consumption. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system's READ# control line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset. 5.4 VPP Trace on Printed Circuit Boards 5.2 RY/BY# and Block Erase, Byte Write, and Lock-Bit Configuration Polling RY/BY# is a full CMOS output that provides a hardware method of detecting block erase, byte write and lock-bit configuration completion. It transitions low after block erase, byte write, or lockbit configuration commands and returns to VOH when the WSM has finished executing the internal algorithm. RY/BY# can be connected to an interrupt input of the system CPU or controller. It is active at all times. RY/BY# is also VOH when the device is in block erase suspend (with byte write inactive), byte write suspend or deep power-down modes. Updating flash memories that reside in the target system requires that the printed circuit board designers pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for byte writing and block erasing. Use similar trace widths and layout considerations given to the VCC power bus. Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots. 5.5 VCC, VPP, RP# Transitions 5.3 Power Supply Decoupling Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current Block erase, byte write and lock-bit configuration are not guaranteed if VPP falls outside of a valid VPPH1/2/3 range, VCC falls outside of a valid VCC2/3/4 range, or RP# VIH or VHH. If VPP error is detected, status register bit SR.3 is set to "1" along with SR.4 or SR.5, depending on the attempted operation. If RP# transitions to VIL during block erase, byte write, or lock-bit configuration, RY/BY# will remain low until the reset operation is complete. Then, the operation will abort and the device will enter deep power-down. The aborted operation may leave data partially altered. Therefore, the command sequence must be repeated after normal - 23 - LH28F016SC-L/SCH-L operation is restored. Device power-off or RP# transitions to VIL clear the status register. The CUI latches commands issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its state is read array mode upon power-up, after exit from deep powerdown or after VCC transitions below VLKO. After block erase, byte write, or lock-bit configuration, even after VPP transitions down to VPPLK, the CUI must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired. 5.7 Power Consumption When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory's nonvolatility increases usable battery life because data is retained when system power is removed. In addition, deep power-down mode ensures extremely low power consumption even when system power is applied. For example, portable computing products and other power sensitive applications that use an array of devices for solidstate storage can consume negligible power by lowering RP# to VIL standby or sleep modes. If access is again needed, the devices can be read following the tPHQV and tPHWL wake-up cycles required after RP# is first raised to VIH. See Section 6.2.4 through 6.2.6 "AC CHARACTERISTICS READ-ONLY and WRITE OPERATIONS" and Fig. 13, Fig. 14 and Fig. 15 for more information. 5.6 Power-Up/Down Protection The device is designed to offer protection against accidental block erasure, byte writing, or lock-bit configuration during power transitions. Upon powerup, the device is indifferent as to which power supply (VPP or VCC) powers-up first. Internal circuitry resets the CUI to read array mode at power-up. A system designer must guard against spurious writes for VCC voltages above VLKO when VPP is active. Since both WE# and CE# must be low for a command write, driving either to VIH will inhibit writes. The CUI's two-step command sequence architecture provides added level of protection against data alteration. In-system block lock and unlock capability prevents inadvertent data alteration. The device is disabled while RP# = VIL regardless of its control inputs state. - 24 - LH28F016SC-L/SCH-L 6 ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings Operating Temperature * LH28F016SC-L During Read, Block Erase, Byte Write and Lock-Bit Configuration ........ 0 to +70C (NOTE 1) Temperature under Bias ............. -10 to +80C * LH28F016SCH-L During Read, Block Erase, Byte Write and Lock-Bit Configuration .... -40 to +85C (NOTE 2) Temperature under Bias............. -40 to +85C Storage Temperature ........................ -65 to +125C Voltage On Any Pin (except VCC, VPP, and RP#) .... -2.0 to +7.0 V (NOTE 3) VCC Supply Voltage ................. -2.0 to +7.0 V (NOTE 3) VPP Update Voltage during Block Erase, Byte Write and Lock-Bit Configuration .. -2.0 to +14.0 V (NOTE 3, 4) RP# Voltage with Respect to GND during Lock-Bit Configuration Operations .. -2.0 to +14.0 V (NOTE 3, 4) Output Short Circuit Current .............. 100 mA (NOTE 5) NOTICE : The specifications are subject to change without notice. Verify with your local SHARP sales office that you have the latest datasheet before finalizing a design. WARNING : Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. NOTES : 1. 2. 3. Operating temperature is for commercial product defined by this specification. Operating temperature is for extended temperature product defined by this specification. All specified voltages are with respect to GND. Minimum DC voltage is -0.5 V on input/output pins and - 0.2 V on VCC and VPP pins. During transitions, this level may undershoot to -2.0 V for periods < 20 ns. Maximum DC voltage on input/output pins and VCC is VCC+0.5 V which, during transitions, may overshoot to VCC+2.0 V for periods < 20 ns. Maximum DC voltage on VPP and RP# may overshoot to +14.0 V for periods < 20 ns. Output shorted for no more than one second. No more than one output shorted at a time. 4. 5. 6.2 TA VCC1 VCC2 VCC3 VCC4 Operating Conditions PARAMETER Operating Temperature VCC Supply Voltage (2.7 to 3.6 V) VCC Supply Voltage (3.30.3 V) VCC Supply Voltage (5.00.25 V) VCC Supply Voltage (5.00.5 V) NOTE 1 2 MIN. 0 -40 2.7 3.0 4.75 4.50 MAX. +70 +85 3.6 3.6 5.25 5.50 UNIT C C V V V V LH28F016SC-L95/SCH-L95 VERSIONS LH28F016SC-L LH28F016SCH-L SYMBOL NOTES : 1. 2. Test condition : Ambient temperature Block erase, byte write and lock-bit configuration operations with VCC < 3.0 V should not be attempted. - 25 - LH28F016SC-L/SCH-L 6.2.1 CAPACITANCE (NOTE 1) TA = +25C, f = 1 MHz SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance TYP. 6 8 MAX. 8 12 UNIT pF pF CONDITION VIN = 0.0 V VOUT = 0.0 V NOTE : 1. Sampled, not 100% tested. 6.2.2 AC INPUT/OUTPUT TEST CONDITIONS 2.7 INPUT 0.0 1.35 TEST POINTS 1.35 OUTPUT AC test inputs are driven at 2.7 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output timing ends, at 1.35 V. Input rise and fall times (10% to 90%) < 10 ns. Fig. 9 Transient Input/Output Reference Waveform for VCC = 2.7 to 3.6 V 3.0 INPUT 0.0 1.5 TEST POINTS 1.5 OUTPUT AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output timing ends, at 1.5 V. Input rise and fall times (10% to 90%) < 10 ns. Fig. 10 Transient Input/Output Reference Waveform for VCC = 3.30.3 V and VCC = 5.00.25 V (High Speed Testing Configuration) 2.4 INPUT 0.45 2.0 TEST POINTS 0.8 2.0 OUTPUT 0.8 AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0". Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) < 10 ns. Fig. 11 Transient Input/Output Reference Waveform for VCC = 5.00.5 V (Standard Testing Configuration) - 26 - LH28F016SC-L/SCH-L Test Configuration Capacitance Loading Value 1.3 V 1N914 TEST CONFIGURATION VCC = 3.30.3 V, 2.7 to 3.6 V VCC = 5.00.25 V (NOTE 1) VCC = 5.00.5 V CL (pF) 50 30 100 NOTE : RL = 3.3 k DEVICE UNDER TEST CL CL Includes Jig Capacitance 1. OUT Applied to high-speed products, LH28F016SC-L95 and LH28F016SCH-L95. Fig. 12 Transient Equivalent Testing Load Circuit - 27 - LH28F016SC-L/SCH-L 6.2.3 DC CHARACTERISTICS SYMBOL ILI ILO PARAMETER Input Load Current Output Leakage Current NOTE 1 1 20 ICCS VCC Standby Current 1, 3, 6 0.1 LH28F016 VCC Deep PowerSC-L Down Current LH28F016 SCH-L 2 10 1 20 20 20 0.2 2 10 0.4 2 10 A VCC = 2.7 to 3.6 V VCC = 3.30.3 V VCC = 5.00.5 V UNIT TYP. MAX. TYP. MAX. TYP. MAX. 0.5 0.5 100 20 0.5 0.5 100 25 1 10 100 TEST CONDITIONS VCC = VCC Max. A VIN = VCC or GND VCC = VCC Max. A VOUT = VCC or GND CMOS Inputs A VCC = VCC Max. CE# = RP# = VCC0.2 V TTL Inputs mA VCC = VCC Max. CE# = RP# = VIH RP# = GND0.2 V IOUT (RY/BY#) = 0 mA CMOS Inputs VCC = VCC Max. CE# = GND f = 5 MHz (3.3 V, 2.7 V), 8 MHz (5 V) IOUT = 0 mA TTL Inputs VCC = VCC Max. CE# = GND f = 5 MHz (3.3 V, 2.7 V), 8 MHz (5 V) IOUT = 0 mA VPP = 3.30.3 V VPP = 5.00.5 V VPP = 12.00.6 V VPP = 3.30.3 V VPP = 5.00.5 V VPP = 12.00.6 V ICCD 6 12 7 12 17 35 mA ICCR VCC Read Current 1, 5, 6 7 18 8 18 20 50 mA ICCW VCC Byte Write or Set Lock-Bit Current 1, 7 VCC Block Erase or Clear Block Lock-Bits Current ICCWS VCC Byte Write or Block ICCES Erase Suspend Current IPPS VPP Standby or IPPR Read Current VPP Deep Power-Down IPPD Current ICCE IPPW VPP Byte Write or Set Lock-Bit Current 1, 7 1, 2 1 1 -- -- -- -- -- -- -- 2 10 0.1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15 200 5 -- -- -- -- -- -- -- 10 1 2 10 0.1 17 17 12 17 17 12 6 15 200 5 40 40 15 20 20 15 200 -- -- -- 35 30 -- 30 25 10 15 200 5 -- 40 15 -- 20 15 200 mA mA mA mA mA mA 1 2 10 0.1 -- mA CE# = VIH A A A mA mA mA mA mA mA A VPP VCC VPP > VCC RP# = GND0.2 V VPP VPP VPP VPP VPP VPP = = = = = = 3.30.3 V 5.00.5 V 12.00.6 V 3.30.3 V 5.00.5 V 12.00.6 V 1, 7 VPP Block Erase or Clear Block Lock-Bits Current IPPWS VPP Byte Write or Block IPPES Erase Suspend Current IPPE -- 1, 7 1 10 VPP = VPPH1/2/3 - 28 - LH28F016SC-L/SCH-L 6.2.3 DC CHARACTERISTICS (contd.) SYMBOL VIL VIH PARAMETER Input Low Voltage Input High Voltage NOTE 7 7 VCC = 2.7 to 3.6 V VCC = 3.30.3 V VCC = 5.00.5 V UNIT MIN. MAX. MIN. MAX. MIN. MAX. - 0.5 - 0.5 - 0.5 0.8 0.8 0.8 V VCC VCC VCC 2.0 2.0 2.0 V +0.5 +0.5 +0.5 0.4 0.4 0.45 V TEST CONDITIONS VOL Output Low Voltage Output High Voltage (TTL) 3, 7 VOH1 3, 7 2.4 0.85 VCC VCC - 0.4 1.5 2.4 0.85 VCC VCC - 0.4 1.5 2.4 0.85 VCC VCC - 0.4 1.5 V VOH2 Output High Voltage (CMOS) V V V 3, 7 VCC = VCC Min. IOL = 5.8 mA (5 V) IOL = 2.0 mA (3.3 V, 2.7 V) VCC = VCC Min. IOH = -2.5 mA (5 V) IOH = -2.0 mA (3.3 V, 2.7 V) VCC = VCC Min. IOH = -2.5 mA VCC = VCC Min. IOH = -100 A VPP Lockout Voltage during 4, 7 Normal Operations VPP Voltage during VPPH1 Byte Write, Block Erase or Lock-Bit Operations VPP Voltage during VPPH2 Byte Write, Block Erase or Lock-Bit Operations VPP Voltage during VPPH3 Byte Write, Block Erase or Lock-Bit Operations VLKO VCC Lockout Voltage VPPLK VHH RP# Unlock Voltage 8, 9 -- -- 3.0 3.6 -- -- V -- -- 4.5 5.5 4.5 5.5 V -- 2.0 -- -- 11.4 2.0 12.6 11.4 2.0 12.6 V V -- 11.4 12.6 11.4 12.6 V Set master lock-bit Override master and block lock-bit NOTES : 1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA = +25C. These currents are valid for all product versions (packages and speeds). ICCWS and ICCES are specified with the device deselected. If reading or byte writing in erase suspend mode, the device's current draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively. Includes RY/BY#. Block erases, byte writes, and lock-bit configurations are inhibited when VPP VPPLK, and not guaranteed in the range between VPPLK (max.) and VPPH1 (min.), between VPPH1 (max.) and VPPH2 (min.), between VPPH2 (max.) and VPPH3 (min.), and above VPPH3 (max.). Automatic Power Saving (APS) reduces typical ICCR to 1 mA at 5 V VCC and 3 mA at 2.7 V and 3.3 V VCC in static operation. 6. 7. 8. CMOS inputs are either VCC0.2 V or GND0.2 V. TTL inputs are either VIL or VIH. Sampled, not 100% tested. Master lock-bit set operations are inhibited when RP# = VIH. Block lock-bit configuration operations are inhibited when the master lock-bit is set and RP# = VIH. Block erases and byte writes are inhibited when the corresponding block lock-bit is set and RP# = VIH. Block erase, byte write, and lock-bit configuration operations are not guaranteed with VCC < 3.0 V or VIH < RP# < VHH and should not be attempted. RP# connection to a VHH supply is allowed for a maximum cumulative period of 80 hours. 2. 3. 4. 9. 5. - 29 - LH28F016SC-L/SCH-L 6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS (NOTE 1) * VCC = 2.7 to 3.6 V, TA = 0 to +70C or -40 to +85C VERSIONS SYMBOL tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH PARAMETER Read Cycle Time Address to Output Delay CE# to Output Delay RP# High to Output Delay OE# to Output Delay CE# to Output in Low Z CE# High to Output in High Z OE# to Output in Low Z OE# High to Output in High Z Output Hold from Address, CE# or OE# Change, Whichever Occurs First 2 2 3 3 3 3 3 NOTE LH28F016SC-L95 LH28F016SCH-L95 MIN. 150 150 150 600 50 0 55 0 20 0 MAX. LH28F016SC-L12 LH28F016SCH-L12 UNIT MIN. 170 170 170 600 55 0 55 0 25 0 MAX. ns ns ns ns ns ns ns ns ns ns * VCC = 3.30.3 V, TA = 0 to +70C or -40 to +85C VERSIONS SYMBOL tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH PARAMETER Read Cycle Time Address to Output Delay CE# to Output Delay RP# High to Output Delay OE# to Output Delay CE# to Output in Low Z CE# High to Output in High Z OE# to Output in Low Z OE# High to Output in High Z Output Hold from Address, CE# or OE# Change, Whichever Occurs First 2 3 3 3 3 3 0 0 20 0 0 55 0 25 NOTE LH28F016SC-L95 LH28F016SCH-L95 MIN. 120 2 120 120 600 50 0 55 MAX. LH28F016SC-L12 LH28F016SCH-L12 UNIT MIN. 150 150 150 600 55 MAX. ns ns ns ns ns ns ns ns ns ns NOTES : 1. 2. 3. See AC Input/Output Reference Waveform (Fig. 9 through Fig. 11) for maximum allowable input slew rate. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. Sampled, not 100% tested. - 30 - LH28F016SC-L/SCH-L 6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS (contd.) (NOTE 1) * VCC = 5.00.25 V, 5.00.5 V, TA = 0 to +70C or -40 to +85C (NOTE 4) VCC0.25 V VERSIONS VCC0.5 V SYMBOL PARAMETER tAVAV Read Cycle Time tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH Address to Output Delay CE# to Output Delay RP# High to Output Delay OE# to Output Delay CE# to Output in Low Z CE# High to Output in High Z OE# to Output in Low Z OE# High to Output in High Z Output Hold from Address, CE# or OE# Change, Whichever Occurs First 2 3 3 3 3 3 NOTE LH28F016SC-L95 LH28F016SCH-L95 (NOTE 5) (NOTE 5) LH28F016SC-L95 LH28F016SC-L12 LH28F016SCH-L95 LH28F016SCH-L12 MIN. 95 MAX. 95 95 400 40 0 55 0 10 0 0 0 10 0 0 55 0 15 MIN. 100 MAX. 100 100 400 45 0 55 MIN. 120 MAX. UNIT ns 120 120 400 50 ns ns ns ns ns ns ns ns ns 2 NOTES : 1. 2. 3. 4. See AC Input/Output Reference Waveform (Fig. 9 through Fig. 11) for maximum allowable input slew rate. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. Sampled, not 100% tested. See Fig. 10 "Transient Input/Output Reference Waveform" and Fig. 12 "Transient Equivalent Testing Load Circuit" (High Speed Configuration) for testing characteristics. 5. See Fig. 11 "Transient Input/Output Reference Waveform" and Fig. 12 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing characteristics. - 31 - LH28F016SC-L/SCH-L Standby VIH ADDRESSES (A) VIL Device Address Selection Address Stable Data Valid tAVAV VIH CE# (E) VIL tEHQZ OE# (G) VIH tGHQZ VIL tELQV VIH WE# (W) VIL tELQX DATA (D/Q) (DQ0 - DQ7) VOH VOL High Z tAVQV tGLQV tGLQX tOH High Z Valid Output VCC tPHQV VIH RP# (P) VIL Fig. 13 AC Waveform for Read Operations - 32 - LH28F016SC-L/SCH-L 6.2.5 AC CHARACTERISTICS - WRITE OPERATION (NOTE 1) * VCC = 2.7 to 3.6 V, TA = 0 to +70C or -40 to +85C VERSIONS SYMBOL PARAMETER tAVAV Write Cycle Time tPHWL tELWL tWLWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHGL RP# High Recovery to WE# Going Low CE# Setup to WE# Going Low WE# Pulse Width Address Setup to WE# Going High Data Setup to WE# Going High Data Hold from WE# High Address Hold from WE# High CE# Hold from WE# High WE# Pulse Width High Write Recovery before Read 3 3 NOTE 2 LH28F016SC-L95 LH28F016SCH-L95 MIN. 150 1 10 50 50 50 5 5 10 30 0 MAX. LH28F016SC-L12 LH28F016SCH-L12 UNIT MIN. MAX. 170 ns 1 10 50 50 50 5 5 10 30 0 s ns ns ns ns ns ns ns ns ns * VCC = 3.30.3 V, TA = 0 to +70C or -40 to +85C VERSIONS SYMBOL PARAMETER tAVAV Write Cycle Time tPHWL tELWL tWLWH tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHRL tWHGL tQVVL tQVPH RP# High Recovery to WE# Going Low CE# Setup to WE# Going Low WE# Pulse Width 2 2 3 3 VPP Setup to WE# Going High Address Setup to WE# Going High Data Setup to WE# Going High Data Hold from WE# High Address Hold from WE# High CE# Hold from WE# High WE# Pulse Width High WE# High to RY/BY# Going Low Write Recovery before Read VPP Hold from Valid SRD, RY/BY# High RP# VHH Hold from Valid SRD, RY/BY# High 2, 4 2, 4 3. 4. LH28F016SC-L95 LH28F016SCH-L95 NOTE 2 MIN. 120 1 10 50 100 100 50 50 5 5 10 30 100 0 0 0 MAX. LH28F016SC-L12 LH28F016SCH-L12 UNIT MIN. MAX. 150 ns 1 10 50 100 100 50 50 5 5 10 30 100 0 0 0 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns tPHHWH RP# VHH Setup to WE# Going High NOTES : 1. Read timing characteristics during block erase, byte write and lock-bit configuration operations are the same as during read-only operations. Refer to Section 6.2.4 "AC CHARACTERISTICS" for read-only operations. Sampled, not 100% tested. Refer to Table 3 for valid AIN and DIN for block erase, byte write, or lock-bit configuration. VPP should be held at VPPH1/2/3 (and if necessary RP# should be held at VHH) until determination of block erase, byte write, or lock-bit configuration success (SR.1/3/4/5 = 0). 2. - 33 - LH28F016SC-L/SCH-L 6.2.5 AC CHARACTERISTICS - WRITE OPERATION (contd.) (NOTE 1) * VCC = 5.00.25 V, 5.00.5 V, TA = 0 to +70C or -40 to +85C (NOTE 5) VCC0.25 V VERSIONS VCC0.5 V SYMBOL PARAMETER tAVAV Write Cycle Time tPHWL tELWL RP# High Recovery to WE# Going Low CE# Setup to WE# Going Low 2 2 3 3 NOTE LH28F016SC-L95 LH28F016SCH-L95 (NOTE 6) (NOTE 6) UNIT LH28F016SC-L95 LH28F016SC-L12 LH28F016SCH-L95 LH28F016SCH-L12 MIN. 95 1 10 40 100 100 40 40 5 5 10 30 90 0 0 0 0 MAX. MIN. 100 1 10 40 100 100 40 40 5 5 10 30 90 0 0 0 MAX. MIN. 120 1 10 40 100 100 40 40 5 5 10 30 90 MAX. ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 tWLWH WE# Pulse Width tPHHWH RP# VHH Setup to WE# Going High tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHRL tWHGL tQVVL tQVPH VPP Setup to WE# Going High Address Setup to WE# Going High Data Setup to WE# Going High Data Hold from WE# High Address Hold from WE# High CE# Hold from WE# High WE# Pulse Width High WE# High to RY/BY# Going Low Write Recovery before Read VPP Hold from Valid SRD, RY/BY# High RP# VHH Hold from Valid SRD, RY/BY# High 2, 4 2, 4 0 0 NOTES : 1. Read timing characteristics during block erase, byte write and lock-bit configuration operations are the same as during read-only operations. Refer to Section 6.2.4 "AC CHARACTERISTICS" for read-only operations. Sampled, not 100% tested. Refer to Table 3 for valid AIN and DIN for block erase, byte write, or lock-bit configuration. VPP should be held at VPPH1/2/3 (and if necessary RP# should be held at VHH) until determination of block erase, byte write, or lock-bit configuration success (SR.1/3/4/5 = 0). 5. See Fig. 10 "Transient Input/Output Reference Waveform" and Fig. 12 "Transient Equivalent Testing Load Circuit" (High Seed Configuration) for testing characteristics. See Fig. 11 "Transient Input/Output Reference Waveform" and Fig. 12 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing characteristics. 2. 3. 4. 6. - 34 - LH28F016SC-L/SCH-L (NOTE 1) (NOTE 2) (NOTE 3) (NOTE 4) (NOTE 5) (NOTE 6) VIH ADDRESSES (A) VIL VIH CE# (E) VIL VIH OE# (G) VIL tWHWL VIH WE# (W) VIL tWLWH tDVWH tWHDX High Z tPHWL tWHRL DIN DIN Valid SRD DIN tWHQV1/2/3/4 tELWL tWHEH tWHGL AIN tAVAV AIN tAVWH tWHAX VIH DATA (D/Q) VIL VOH RY/BY# (R) VOL tPHHWH VHH RP# (P) VIH VIL tVPWH VPPH1/2/3 VPP (V) VPPLK VIL tQVPH tQVVL NOTES : 1. 2. 3. 4. 5. 6. VCC power-up and standby. Write block erase or byte write setup. Write block erase confirm or valid address and data. Automated erase or program delay. Read status register data. Write Read Array command. Fig. 14 AC Waveform for WE#-Controlled Write Operations - 35 - LH28F016SC-L/SCH-L 6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES (NOTE 1) * VCC = 2.7 to 3.6 V, TA = 0 to +70C or -40 to +85C VERSIONS SYMBOL tAVAV tPHEL tWLEL tELEH tAVEH tDVEH tEHDX tEHAX tEHWH tEHEL tEHGL PARAMETER Write Cycle Time RP# High Recovery to CE# Going Low WE# Setup to CE# Going Low CE# Pulse Width Address Setup to CE# Going High Data Setup to CE# Going High Data Hold from CE# High Address Hold from CE# High WE# Hold from CE# High CE# Pulse Width High Write Recovery before Read 3 3 2 NOTE LH28F016SC-L95 LH28F016SCH-L95 MIN. 150 1 0 70 50 50 5 5 0 25 0 MAX. LH28F016SC-L12 LH28F016SCH-L12 UNIT MIN. 170 1 0 70 50 50 5 5 0 25 0 MAX. ns s ns ns ns ns ns ns ns ns ns * VCC = 3.30.3 V, TA = 0 to +70C or -40 to +85C VERSIONS SYMBOL PARAMETER tAVAV Write Cycle Time tPHEL tWLEL tELEH tPHHEH tVPEH tAVEH tDVEH tEHDX tEHAX tEHWH tEHEL tEHRL tEHGL tQVVL tQVPH RP# High Recovery to CE# Going Low WE# Setup to CE# Going Low CE# Pulse Width RP# VHH Setup to CE# Going High VPP Setup to CE# Going High Address Setup to CE# Going High Data Setup to CE# Going High Data Hold from CE# High Address Hold from CE# High WE# Hold from CE# High CE# Pulse Width High CE# High to RY/BY# Going Low Write Recovery before Read VPP Hold from Valid SRD, RY/BY# High RP# VHH Hold from Valid SRD, RY/BY# High 2, 4 2, 4 3. 4. LH28F016SC-L95 LH28F016SCH-L95 NOTE 2 MIN. 120 1 0 70 2 2 3 3 100 100 50 50 5 5 0 25 100 0 0 0 MAX. LH28F016SC-L12 LH28F016SCH-L12 UNIT MIN. 150 1 0 70 100 100 50 50 5 5 0 25 100 0 0 0 MAX. ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES : 1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive WE# times should be measured relative to the CE# waveform. Sampled, not 100% tested. Refer to Table 3 for valid AIN and DIN for block erase, byte write, or lock-bit configuration. VPP should be held at VPPH1/2/3 (and if necessary RP# should be held at VHH) until determination of block erase, byte write, or lock-bit configuration success (SR.1/3/4/5 = 0). 2. - 36 - LH28F016SC-L/SCH-L 6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES (contd.) (NOTE 1) * VCC = 5.00.25 V, 5.00.5 V, TA = 0 to +70C or -40 to +85C (NOTE 5) VCC0.25 V VERSIONS VCC0.5 V SYMBOL PARAMETER tAVAV Write Cycle Time tPHEL tWLEL tELEH tPHHEH tVPEH tAVEH tDVEH tEHDX tEHAX tEHWH tEHEL tEHRL tEHGL tQVVL tQVPH RP# High Recovery to CE# Going Low WE# Setup to CE# Going Low CE# Pulse Width RP# VHH Setup to CE# Going High VPP Setup to CE# Going High Address Setup to CE# Going High Data Setup to CE# Going High Data Hold from CE# High Address Hold from CE# High WE# Hold from CE# High CE# Pulse Width High CE# High to RY/BY# Going Low Write Recovery before Read VPP Hold from Valid SRD, RY/BY# High RP# VHH Hold from Valid SRD, RY/BY# High 2, 4 2, 4 2 2 3 3 NOTE LH28F016SC-L95 LH28F016SCH-L95 (NOTE 6) (NOTE 6) UNIT LH28F016SC-L95 LH28F016SC-L12 LH28F016SCH-L95 LH28F016SCH-L12 MIN. 95 1 0 50 100 100 40 40 5 5 0 25 90 0 0 0 0 0 0 MAX. MIN. 100 1 0 50 100 100 40 40 5 5 0 25 90 0 0 0 MAX. MIN. 120 1 0 50 100 100 40 40 5 5 0 25 90 MAX. ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 NOTES : 1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive WE# times should be measured relative to the CE# waveform. Sampled, not 100% tested. Refer to Table 3 for valid AIN and DIN for block erase, byte write, or lock-bit configuration. VPP should be held at VPPH1/2/3 (and if necessary RP# should be held at VHH) until determination of block erase, byte write, or lock-bit configuration success (SR.1/3/4/5 = 0). 5. See Fig. 10 "Transient Input/Output Reference Waveform" and Fig. 12 "Transient Equivalent Testing Load Circuit" (High Seed Configuration) for testing characteristics. See Fig. 11 "Transient Input/Output Reference Waveform" and Fig. 12 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing characteristics. 2. 3. 4. 6. - 37 - LH28F016SC-L/SCH-L (NOTE 1) (NOTE 2) (NOTE 3) (NOTE 4) (NOTE 5) (NOTE 6) VIH ADDRESSES (A) VIL VIH WE# (W) VIL VIH OE# (G) VIL tEHEL VIH CE# (E) VIL tELEH tDVEH tEHDX High Z tPHEL tEHRL DIN DIN Valid SRD DIN tEHQV1/2/3/4 tWLEL tEHWH tEHGL AIN tAVAV AIN tAVEH tEHAX VIH DATA (D/Q) VIL VOH RY/BY# (R) VOL tPHHEH VHH RP# (P) VIH VIL tVPEH VPPH1/2/3 VPP (V) VPPLK VIL tQVPH tQVVL NOTES : 1. 2. 3. 4. 5. 6. VCC power-up and standby. Write block erase or byte write setup. Write block erase confirm or valid address and data. Automated erase or program delay. Read status register data. Write Read Array command. Fig. 15 AC Waveform for CE#-Controlled Write Operations - 38 - LH28F016SC-L/SCH-L 6.2.7 RESET OPERATIONS VOH RY/BY# (R) VOL VIH RP# (P) VIL tPLPH (A) Reset During Read Array Mode VOH RY/BY# (R) VOL VIH RP# (P) VIL tPLPH (B) Reset During Block Erase, Byte Write, or Lock-Bit Configuration tPLRH 2.7 V/3.3 V/5 V VCC VIL VIH RP# (P) VIL (C) RP# Rising Timing t235VPH Fig. 16 AC Waveform for Reset Operation Reset AC Specifications (NOTE 1) SYMBOL tPLPH PARAMETER NOTE VCC = 2.7 to 3.6 V MIN. MAX. 100 VCC = 3.30.3 V MIN. MAX. 100 VCC = 5.00.5 V MIN. MAX. 100 UNIT ns RP# Pulse Low Time (If RP# is tied to VCC, this specification is not applicable) RP# Low to Reset during tPLRH Block Erase, Byte Write or Lock-Bit Configuration VCC 2.7 V to RP# High t235VPH VCC 3.0 V to RP# High VCC 4.5 V to RP# High 2, 3 -- 20 12 s 4 100 100 100 ns NOTES : 1. 2. These specifications are valid for all product versions (packages and speeds). If RP# is asserted while a block erase, byte write, or lock-bit configuration operation is not executing, the reset will complete within 100 ns. 3. 4. A reset time, tPHQV, is required from the latter of RY/BY# or RP# going high until outputs are valid. When the device power-up, holding RP#-low minimum 100 ns is required after VCC has been in predefined range and also has been in stable there. - 39 - LH28F016SC-L/SCH-L 6.2.8 BLOCK ERASE, BYTE WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE (NOTE 3, 4) * VCC = 3.30.3 V, TA = 0 to +70C or -40 to +85C VPP = 3.30.3 V SYMBOL PARAMETER NOTE MIN. TYP.(NOTE 1) MAX. tWHQV1 Byte Write Time tEHQV1 Block Write Time tWHQV2 tEHQV2 Block Erase Time 2 2 2 2 2 15 1 1.5 18 1.5 17 1.1 1.8 21 1.8 7.1 15.2 TBD TBD TBD TBD TBD 10 21.1 VPP = 5.00.5 V MIN. 8.2 0.5 1 11.2 1 TYP.(NOTE 1) 9.3 0.5 1.2 13.3 1.2 6.6 12.3 MAX. TBD TBD TBD TBD TBD 9.3 17.2 VPP = 12.00.6 V MIN. TYP.(NOTE 1) MAX. 6.7 0.4 0.8 9.7 0.8 7.6 0.5 1.1 11.6 1.1 7.4 12.3 TBD TBD TBD TBD TBD 10.4 17.2 UNIT s s s s s s s tWHQV3 Set Lock-Bit Time tEHQV3 tWHQV4 Clear Block Lock-Bits tEHQV4 Time tWHRH1 Byte Write Suspend tEHRH1 Latency Time to Read tWHRH2 Erase Suspend Latency tEHRH2 Time to Read * VCC = 5.00.25 V, 5.00.5 V, TA = 0 to +70C or -40 to +85C SYMBOL tWHQV1 tEHQV1 tWHQV2 tEHQV2 tWHQV3 tEHQV3 tWHQV4 tEHQV4 tWHRH1 tEHRH1 tWHRH2 tEHRH2 PARAMETER Byte Write Time Block Write Time Block Erase Time Set Lock-Bit Time Clear Block Lock-Bits Time Byte Write Suspend Latency Time to Read Erase Suspend Latency Time to Read NOTE 2 2 2 2 2 VPP = 5.00.5 V MIN. TYP.(NOTE 1) MAX. 6.5 0.4 0.9 9.5 0.9 8 0.5 1.1 12 1.1 5.6 9.4 TBD TBD TBD TBD TBD 7 13.1 VPP = 12.00.6 V MIN. TYP.(NOTE 1) MAX. 4.8 0.3 0.3 7.8 0.3 6 0.4 1.0 10 1.0 5.2 9.8 TBD TBD TBD TBD TBD 7.5 12.6 UNIT s s s s s s s NOTES : 1. Typical values measured at TA = +25C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. Excludes system-level overhead. 3. 4. These performance numbers are valid for all speed versions. Sampled, not 100% tested. 2. - 40 - LH28F016SC-L/SCH-L 7 ORDERING INFORMATION Product line designator for all SHARP Flash products L H 2 8 F 0 1 6 S C (H) T - L 9 5 Device Density 016 = 16 M-bit Architecture S = Symmetrical Block Power Supply Type C = SmartVoltage Technology Operating Temperature Blank = 0 to +70C H = - 40 to +85C Access Speed (ns) 95 : 95 ns (5.00.25 V), 100 ns (5.00.5 V), 120 ns (3.30.3 V), 150 ns (2.7 to 3.6 V) 12 : 120 ns (5.00.5 V), 150 ns (3.30.3 V), 170 ns (2.7 to 3.6 V) Package T = 40-pin TSOP (I) (TSOP040-P-1020) Normal bend R = 40-pin TSOP (I) (TSOP040-P-1020) Reverse bend N = 44-pin SOP (SOP044-P-0600) [LH28F016SC-L] B = 48-ball CSP (FBGA048-P-0810) VALID OPERATIONAL COMBINATIONS OPTION ORDER CODE VCC = 2.7 to 3.6 V 50 pF load, 1.35 V I/O Levels 1 2 LH28F016SCXX-L95 LH28F016SCXX-L12 150 ns 170 ns VCC = 3.30.3 V 50 pF load, 1.5 V I/O Levels 120 ns 150 ns VCC = 5.0 0.5 V 100 pF load, TTL I/O Levels 100 ns 120 ns VCC = 5.0 0.25 V 30 pF load, 1.5 V I/O Levels 95 ns - 41 - 0.125 0.05 1 40 TSOP (TSOP040-P-1020) 20 20.0 0.3 0.115 0.1 19.00.3 0.125 0.435 0.995 0.1 1.20MAX. Package base plane 18.40.2 40 21 P _ 0.5 TYP. 0.08 10.0 0.2 0.10 40 _ 0.2 0.08 M PACKAGING PACKAGING 44 SOP (SOP044-P-0600) 44_ 0.40.1 1.27TYP. 0.15 M 44 23 16.0 0.4 13.2 0.2 2.7 0.2 1 1.275 28.2 0.2 22 0.15 0.15 0.05 Package base plane 0.1 0.150.1 (14.4) PACKAGING 48 CSP (FBGA048-P-0810) B A / / 0.1 S S 0.4TYP. 0.350.05 10.00 + 0.2 1.2MAX. 8.00 + 0.2 Land hole diameter for ball mounting 0.1 S C 3.0TYP. 0.8TYP. 0.4TYP. 0.4TYP. 0.8TYP. 1.2TYP. H D A 1 6 0.450.03 0.30 0.15 M M S S AB CD |
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